Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Devices.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Devices.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Devices.txt	(revision 1559)
@@ -17,38 +17,40 @@
 powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225670400000;20;
 powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225675800000;30;
-powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225684800000;20;
-powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225686600000;15;
+powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225683000000;20;
+powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225684800000;15;
 powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225690800000;10;
 powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225699200000;5;
 powerConsumption;rack_1/BladeEnclosure_2/Fan_2;1225706400000;0;
-mean: 15.53030303030303 sum: 170.83333333333334
+mean: 14.848484848484848 sum: 163.33333333333334
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225666800000;0;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225668600000;400;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225670400000;800;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225675800000;1,200;
-airFlow;rack_1/BladeEnclosure_2/Fan_2;1225684800000;800;
-airFlow;rack_1/BladeEnclosure_2/Fan_2;1225686600000;600;
+airFlow;rack_1/BladeEnclosure_2/Fan_2;1225683000000;800;
+airFlow;rack_1/BladeEnclosure_2/Fan_2;1225684800000;600;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225690800000;400;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225699200000;200;
 airFlow;rack_1/BladeEnclosure_2/Fan_2;1225706400000;0;
-mean: 621.2121212121212
+mean: 593.939393939394
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225666800000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225676400000;5;
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225678400000;15;
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225679000000;20;
-powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225685600000;15;
-powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225689800000;10;
+powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225686200000;15;
+powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225690800000;10;
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225703600000;5;
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225704200000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Fan_3;1225706400000;0;
-mean: 8.712121212121213 sum: 95.83333333333333
+mean: 9.166666666666666 sum: 100.83333333333333
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225666800000;0;
+airFlow;rack_1/BladeEnclosure_3/Fan_3;1225676400000;200;
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225678400000;600;
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225679000000;800;
-airFlow;rack_1/BladeEnclosure_3/Fan_3;1225685600000;600;
-airFlow;rack_1/BladeEnclosure_3/Fan_3;1225689800000;400;
+airFlow;rack_1/BladeEnclosure_3/Fan_3;1225686200000;600;
+airFlow;rack_1/BladeEnclosure_3/Fan_3;1225690800000;400;
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225703600000;200;
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225704200000;0;
 airFlow;rack_1/BladeEnclosure_3/Fan_3;1225706400000;0;
-mean: 348.4848484848485
+mean: 366.66666666666663
 powerConsumption;rack_1/BladeEnclosure_4/Fan_4;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_4/Fan_4;1225706400000;0;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceUtilization.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceUtilization.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceUtilization.txt	(revision 1559)
@@ -3,9 +3,9 @@
 utlization;rack_1;1225670400000;0.298;
 utlization;rack_1;1225674000000;0.274;
-utlization;rack_1;1225675800000;0.31;
-utlization;rack_1;1225676400000;0.333;
-utlization;rack_1;1225678400000;0.405;
-utlization;rack_1;1225679000000;0.44;
-utlization;rack_1;1225681200000;0.357;
+utlization;rack_1;1225675800000;0.321;
+utlization;rack_1;1225676400000;0.345;
+utlization;rack_1;1225678400000;0.417;
+utlization;rack_1;1225679000000;0.452;
+utlization;rack_1;1225681200000;0.369;
 utlization;rack_1;1225683000000;0.345;
 utlization;rack_1;1225684800000;0.286;
@@ -24,5 +24,5 @@
 utlization;rack_1;1225704200000;0.024;
 utlization;rack_1;1225706400000;0;
-mean: 0.20995670995670995
+mean: 0.2121212121212121
 utlization;rack_1/BladeEnclosure_1;1225666800000;0.929;
 utlization;rack_1/BladeEnclosure_1;1225668600000;1;
@@ -40,27 +40,30 @@
 utlization;rack_1/BladeEnclosure_2;1225668600000;0.214;
 utlization;rack_1/BladeEnclosure_2;1225670400000;0.786;
-utlization;rack_1/BladeEnclosure_2;1225675800000;0.857;
+utlization;rack_1/BladeEnclosure_2;1225675800000;0.929;
 utlization;rack_1/BladeEnclosure_2;1225676400000;1;
 utlization;rack_1/BladeEnclosure_2;1225681200000;0.857;
-utlization;rack_1/BladeEnclosure_2;1225684800000;0.643;
-utlization;rack_1/BladeEnclosure_2;1225686600000;0.571;
-utlization;rack_1/BladeEnclosure_2;1225690200000;0.5;
+utlization;rack_1/BladeEnclosure_2;1225683000000;0.786;
+utlization;rack_1/BladeEnclosure_2;1225684800000;0.571;
+utlization;rack_1/BladeEnclosure_2;1225686600000;0.5;
+utlization;rack_1/BladeEnclosure_2;1225690200000;0.429;
 utlization;rack_1/BladeEnclosure_2;1225690800000;0.357;
 utlization;rack_1/BladeEnclosure_2;1225693800000;0.214;
 utlization;rack_1/BladeEnclosure_2;1225699200000;0.071;
 utlization;rack_1/BladeEnclosure_2;1225706400000;0;
-mean: 0.48701298701298695
+mean: 0.474025974025974
 utlization;rack_1/BladeEnclosure_3;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3;1225678400000;0.429;
-utlization;rack_1/BladeEnclosure_3;1225679000000;0.643;
-utlization;rack_1/BladeEnclosure_3;1225685600000;0.571;
-utlization;rack_1/BladeEnclosure_3;1225686200000;0.5;
-utlization;rack_1/BladeEnclosure_3;1225689200000;0.429;
-utlization;rack_1/BladeEnclosure_3;1225689800000;0.357;
+utlization;rack_1/BladeEnclosure_3;1225676400000;0.071;
+utlization;rack_1/BladeEnclosure_3;1225678400000;0.5;
+utlization;rack_1/BladeEnclosure_3;1225679000000;0.714;
+utlization;rack_1/BladeEnclosure_3;1225685600000;0.643;
+utlization;rack_1/BladeEnclosure_3;1225686200000;0.571;
+utlization;rack_1/BladeEnclosure_3;1225689200000;0.5;
+utlization;rack_1/BladeEnclosure_3;1225689800000;0.429;
+utlization;rack_1/BladeEnclosure_3;1225690800000;0.357;
 utlization;rack_1/BladeEnclosure_3;1225692800000;0.214;
 utlization;rack_1/BladeEnclosure_3;1225703600000;0.071;
 utlization;rack_1/BladeEnclosure_3;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3;1225706400000;0;
-mean: 0.2532467532467532
+mean: 0.2792207792207792
 utlization;rack_1/BladeEnclosure_4;1225666800000;0;
 utlization;rack_1/BladeEnclosure_4;1225706400000;0;
@@ -93,7 +96,6 @@
 mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_6;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_7;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_7;1225681200000;0;
@@ -107,10 +109,11 @@
 utlization;rack_1/BladeEnclosure_1/Node_9;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9;1225706400000;0;
+mean: 0.36363636363636365
+utlization;rack_1/BladeEnclosure_1/Node_10;1225666800000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10;1225684800000;0;
+utlization;rack_1/BladeEnclosure_1/Node_10;1225706400000;0;
 mean: 0.45454545454545453
-utlization;rack_1/BladeEnclosure_1/Node_10;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_10;1225706400000;0;
-mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_11;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_11;1225681200000;0;
@@ -124,7 +127,7 @@
 utlization;rack_1/BladeEnclosure_1/Node_13;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_14;1225666800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_14;1225668600000;1;
@@ -159,12 +162,11 @@
 utlization;rack_1/BladeEnclosure_2/Node_20;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_21;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909091
 utlization;rack_1/BladeEnclosure_2/Node_22;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_22;1225670400000;1;
@@ -179,6 +181,7 @@
 utlization;rack_1/BladeEnclosure_2/Node_24;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24;1225670400000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24;1225706400000;0;
-mean: 0.9090909090909091
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_25;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_25;1225670400000;1;
@@ -188,12 +191,12 @@
 utlization;rack_1/BladeEnclosure_2/Node_26;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_27;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_28;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_28;1225676400000;1;
@@ -202,51 +205,53 @@
 mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_30;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_31;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_32;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_33;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_34;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_35;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_36;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_37;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_38;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_39;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_39;1225706400000;0;
@@ -468,19 +473,15 @@
 mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_7/Processor_25;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_7/Processor_25;1225681200000;0;
@@ -518,37 +519,41 @@
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225706400000;0;
+mean: 0.36363636363636365
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225666800000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225684800000;0;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225706400000;0;
 mean: 0.45454545454545453
-utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225666800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225706400000;0;
-mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225666800000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225666800000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225666800000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_11/Processor_41;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_11/Processor_41;1225681200000;0;
@@ -586,25 +591,25 @@
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_14/Processor_53;1225666800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_14/Processor_53;1225668600000;1;
@@ -729,42 +734,38 @@
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909091
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909091
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909091
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225670400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909091
 utlization;rack_1/BladeEnclosure_2/Node_22/Processor_85;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_22/Processor_85;1225670400000;1;
@@ -809,18 +810,22 @@
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225670400000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225706400000;0;
-mean: 0.9090909090909091
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225670400000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225706400000;0;
-mean: 0.9090909090909091
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225670400000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225706400000;0;
-mean: 0.9090909090909091
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225670400000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225706400000;0;
-mean: 0.9090909090909091
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_25/Processor_97;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_25/Processor_97;1225670400000;1;
@@ -845,42 +850,42 @@
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_28/Processor_109;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_28/Processor_109;1225676400000;1;
@@ -904,195 +909,203 @@
 mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_39/Processor_153;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_39/Processor_153;1225706400000;0;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Simulation.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Simulation.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Simulation.txt	(revision 1559)
@@ -4,11 +4,11 @@
 Makespan;39,600;0;0;39,600;39,600;39,600;1;
 Resources queue length;0.308;0;0;0.308;0.308;0.308;1;
-Resources total load;0.21;0;0;0.21;0.21;0.21;1;
-Energy usage;1,732.143;2,234.998;4,995,216.837;0;8,250;145,500;84;
-Task completion time;20,008.163;9,216.22;84,938,708.871;7,200;39,600;980,400;49;
-Task execution time;14,253.061;7,661.276;58,695,143.69;7,200;28,800;698,400;49;
-Task start time;0;0;0;0;0;0;49;
-Task flow time;14,253.061;7,661.276;58,695,143.69;7,200;28,800;698,400;49;
-Task waiting time;0;0;0;0;0;0;49;
-Task lateness;0;0;0;0;0;0;49;
-Task tardiness;0;0;0;0;0;0;49;
+Resources total load;0.212;0;0;0.212;0.212;0.212;1;
+Energy usage;1,750;2,227.066;4,959,821.429;0;8,250;147,000;84;
+Task completion time;19,932;9,139.156;83,524,176;7,200;39,600;996,600;50;
+Task execution time;14,112;7,648.285;58,496,256;7,200;28,800;705,600;50;
+Task start time;0;0;0;0;0;0;50;
+Task flow time;14,112;7,648.285;58,496,256;7,200;28,800;705,600;50;
+Task waiting time;0;0;0;0;0;0;50;
+Task lateness;0;0;0;0;0;0;50;
+Task tardiness;0;0;0;0;0;0;50;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Tasks.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Tasks.txt	(revision 1486)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Tasks.txt	(revision 1559)
@@ -1,50 +1,51 @@
 JobID;TaskID;UserDN;SchedName;CpuCnt;ExecStartDate;ExecFinishDate;ExecEndDate;GB_SubDate;LB_SubDate;CompletionTime;ExecStartTime;ExecutionTime;ReadyTime;StartTime;FlowTime;WaitingTime;GQ_WaitingTime;Lateness;Tardiness;ReservStartDate;ReservFinishDate;HostNames;ProcessorName;Energy;AppName;
-1;1;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_1];[rack_1/BladeEnclosure_1/Node_1/Processor_2, rack_1/BladeEnclosure_1/Node_1/Processor_1, rack_1/BladeEnclosure_1/Node_1/Processor_4, rack_1/BladeEnclosure_1/Node_1/Processor_3];0;null;
-2;2;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_2];[rack_1/BladeEnclosure_1/Node_2/Processor_7, rack_1/BladeEnclosure_1/Node_2/Processor_6, rack_1/BladeEnclosure_1/Node_2/Processor_8, rack_1/BladeEnclosure_1/Node_2/Processor_5];0;null;
-3;3;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_3];[rack_1/BladeEnclosure_1/Node_3/Processor_12, rack_1/BladeEnclosure_1/Node_3/Processor_10, rack_1/BladeEnclosure_1/Node_3/Processor_11, rack_1/BladeEnclosure_1/Node_3/Processor_9];0;null;
-4;4;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_4];[rack_1/BladeEnclosure_1/Node_4/Processor_16, rack_1/BladeEnclosure_1/Node_4/Processor_15, rack_1/BladeEnclosure_1/Node_4/Processor_14, rack_1/BladeEnclosure_1/Node_4/Processor_13];0;null;
-5;5;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_5];[rack_1/BladeEnclosure_1/Node_5/Processor_20, rack_1/BladeEnclosure_1/Node_5/Processor_19, rack_1/BladeEnclosure_1/Node_5/Processor_18, rack_1/BladeEnclosure_1/Node_5/Processor_17];0;null;
-6;6;-1;cluster;4;1225666800;1225677600;1225677600;1225666800;1225666800;10800;0;10800;0;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_6];[rack_1/BladeEnclosure_1/Node_6/Processor_24, rack_1/BladeEnclosure_1/Node_6/Processor_22, rack_1/BladeEnclosure_1/Node_6/Processor_23, rack_1/BladeEnclosure_1/Node_6/Processor_21];0;null;
-7;7;-1;cluster;4;1225666800;1225681200;1225681200;1225666800;1225666800;14400;0;14400;0;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_7];[rack_1/BladeEnclosure_1/Node_7/Processor_25, rack_1/BladeEnclosure_1/Node_7/Processor_26, rack_1/BladeEnclosure_1/Node_7/Processor_27, rack_1/BladeEnclosure_1/Node_7/Processor_28];0;null;
-8;8;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_8];[rack_1/BladeEnclosure_1/Node_8/Processor_29, rack_1/BladeEnclosure_1/Node_8/Processor_31, rack_1/BladeEnclosure_1/Node_8/Processor_32, rack_1/BladeEnclosure_1/Node_8/Processor_30];0;null;
-9;9;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_9];[rack_1/BladeEnclosure_1/Node_9/Processor_33, rack_1/BladeEnclosure_1/Node_9/Processor_35, rack_1/BladeEnclosure_1/Node_9/Processor_34, rack_1/BladeEnclosure_1/Node_9/Processor_36];0;null;
-10;10;-1;cluster;4;1225666800;1225677600;1225677600;1225666800;1225666800;10800;0;10800;0;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_10];[rack_1/BladeEnclosure_1/Node_10/Processor_40, rack_1/BladeEnclosure_1/Node_10/Processor_37, rack_1/BladeEnclosure_1/Node_10/Processor_38, rack_1/BladeEnclosure_1/Node_10/Processor_39];0;null;
+1;1;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_1];[rack_1/BladeEnclosure_1/Node_1/Processor_4, rack_1/BladeEnclosure_1/Node_1/Processor_3, rack_1/BladeEnclosure_1/Node_1/Processor_2, rack_1/BladeEnclosure_1/Node_1/Processor_1];0;null;
+2;2;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_2];[rack_1/BladeEnclosure_1/Node_2/Processor_5, rack_1/BladeEnclosure_1/Node_2/Processor_6, rack_1/BladeEnclosure_1/Node_2/Processor_7, rack_1/BladeEnclosure_1/Node_2/Processor_8];0;null;
+3;3;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_3];[rack_1/BladeEnclosure_1/Node_3/Processor_10, rack_1/BladeEnclosure_1/Node_3/Processor_11, rack_1/BladeEnclosure_1/Node_3/Processor_12, rack_1/BladeEnclosure_1/Node_3/Processor_9];0;null;
+4;4;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_4];[rack_1/BladeEnclosure_1/Node_4/Processor_15, rack_1/BladeEnclosure_1/Node_4/Processor_16, rack_1/BladeEnclosure_1/Node_4/Processor_13, rack_1/BladeEnclosure_1/Node_4/Processor_14];0;null;
+5;5;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_5];[rack_1/BladeEnclosure_1/Node_5/Processor_20, rack_1/BladeEnclosure_1/Node_5/Processor_17, rack_1/BladeEnclosure_1/Node_5/Processor_18, rack_1/BladeEnclosure_1/Node_5/Processor_19];0;null;
+6;6;-1;cluster;4;1225666800;1225677600;1225677600;1225666800;1225666800;10800;0;10800;0;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_6];[rack_1/BladeEnclosure_1/Node_6/Processor_21, rack_1/BladeEnclosure_1/Node_6/Processor_23, rack_1/BladeEnclosure_1/Node_6/Processor_22, rack_1/BladeEnclosure_1/Node_6/Processor_24];0;null;
+7;7;-1;cluster;4;1225666800;1225681200;1225681200;1225666800;1225666800;14400;0;14400;0;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_7];[rack_1/BladeEnclosure_1/Node_7/Processor_28, rack_1/BladeEnclosure_1/Node_7/Processor_27, rack_1/BladeEnclosure_1/Node_7/Processor_26, rack_1/BladeEnclosure_1/Node_7/Processor_25];0;null;
+8;8;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_8];[rack_1/BladeEnclosure_1/Node_8/Processor_29, rack_1/BladeEnclosure_1/Node_8/Processor_30, rack_1/BladeEnclosure_1/Node_8/Processor_32, rack_1/BladeEnclosure_1/Node_8/Processor_31];0;null;
+9;9;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_9];[rack_1/BladeEnclosure_1/Node_9/Processor_33, rack_1/BladeEnclosure_1/Node_9/Processor_36, rack_1/BladeEnclosure_1/Node_9/Processor_35, rack_1/BladeEnclosure_1/Node_9/Processor_34];0;null;
+10;10;-1;cluster;4;1225666800;1225677600;1225677600;1225666800;1225666800;10800;0;10800;0;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_10];[rack_1/BladeEnclosure_1/Node_10/Processor_40, rack_1/BladeEnclosure_1/Node_10/Processor_37, rack_1/BladeEnclosure_1/Node_10/Processor_39, rack_1/BladeEnclosure_1/Node_10/Processor_38];0;null;
 11;11;-1;cluster;4;1225666800;1225681200;1225681200;1225666800;1225666800;14400;0;14400;0;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_11];[rack_1/BladeEnclosure_1/Node_11/Processor_43, rack_1/BladeEnclosure_1/Node_11/Processor_42, rack_1/BladeEnclosure_1/Node_11/Processor_41, rack_1/BladeEnclosure_1/Node_11/Processor_44];0;null;
-12;12;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_12];[rack_1/BladeEnclosure_1/Node_12/Processor_48, rack_1/BladeEnclosure_1/Node_12/Processor_47, rack_1/BladeEnclosure_1/Node_12/Processor_46, rack_1/BladeEnclosure_1/Node_12/Processor_45];0;null;
+12;12;-1;cluster;4;1225666800;1225695600;1225695600;1225666800;1225666800;28800;0;28800;0;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_12];[rack_1/BladeEnclosure_1/Node_12/Processor_45, rack_1/BladeEnclosure_1/Node_12/Processor_46, rack_1/BladeEnclosure_1/Node_12/Processor_47, rack_1/BladeEnclosure_1/Node_12/Processor_48];0;null;
 13;13;-1;cluster;4;1225666800;1225674000;1225674000;1225666800;1225666800;7200;0;7200;0;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_13];[rack_1/BladeEnclosure_1/Node_13/Processor_51, rack_1/BladeEnclosure_1/Node_13/Processor_52, rack_1/BladeEnclosure_1/Node_13/Processor_50, rack_1/BladeEnclosure_1/Node_13/Processor_49];0;null;
-14;14;-1;cluster;4;1225668600;1225690200;1225690200;1225668600;1225668600;23400;1800;21600;1800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_14];[rack_1/BladeEnclosure_1/Node_14/Processor_54, rack_1/BladeEnclosure_1/Node_14/Processor_55, rack_1/BladeEnclosure_1/Node_14/Processor_56, rack_1/BladeEnclosure_1/Node_14/Processor_53];0;null;
-15;15;-1;cluster;4;1225668600;1225693800;1225693800;1225668600;1225668600;27000;1800;25200;1800;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_15];[rack_1/BladeEnclosure_2/Node_15/Processor_58, rack_1/BladeEnclosure_2/Node_15/Processor_59, rack_1/BladeEnclosure_2/Node_15/Processor_60, rack_1/BladeEnclosure_2/Node_15/Processor_57];0;null;
-16;16;-1;cluster;4;1225668600;1225690200;1225690200;1225668600;1225668600;23400;1800;21600;1800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_16];[rack_1/BladeEnclosure_2/Node_16/Processor_64, rack_1/BladeEnclosure_2/Node_16/Processor_61, rack_1/BladeEnclosure_2/Node_16/Processor_62, rack_1/BladeEnclosure_2/Node_16/Processor_63];0;null;
-17;17;-1;cluster;4;1225668600;1225693800;1225693800;1225668600;1225668600;27000;1800;25200;1800;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_17];[rack_1/BladeEnclosure_2/Node_17/Processor_67, rack_1/BladeEnclosure_2/Node_17/Processor_68, rack_1/BladeEnclosure_2/Node_17/Processor_65, rack_1/BladeEnclosure_2/Node_17/Processor_66];0;null;
-18;18;-1;cluster;4;1225670400;1225684800;1225684800;1225670400;1225670400;18000;3600;14400;3600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_18];[rack_1/BladeEnclosure_2/Node_18/Processor_70, rack_1/BladeEnclosure_2/Node_18/Processor_72, rack_1/BladeEnclosure_2/Node_18/Processor_71, rack_1/BladeEnclosure_2/Node_18/Processor_69];0;null;
-19;19;-1;cluster;4;1225670400;1225681200;1225681200;1225670400;1225670400;14400;3600;10800;3600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_19];[rack_1/BladeEnclosure_2/Node_19/Processor_75, rack_1/BladeEnclosure_2/Node_19/Processor_74, rack_1/BladeEnclosure_2/Node_19/Processor_76, rack_1/BladeEnclosure_2/Node_19/Processor_73];0;null;
+14;14;-1;cluster;4;1225668600;1225690200;1225690200;1225668600;1225668600;23400;1800;21600;1800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_14];[rack_1/BladeEnclosure_1/Node_14/Processor_53, rack_1/BladeEnclosure_1/Node_14/Processor_54, rack_1/BladeEnclosure_1/Node_14/Processor_55, rack_1/BladeEnclosure_1/Node_14/Processor_56];0;null;
+15;15;-1;cluster;4;1225668600;1225693800;1225693800;1225668600;1225668600;27000;1800;25200;1800;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_15];[rack_1/BladeEnclosure_2/Node_15/Processor_60, rack_1/BladeEnclosure_2/Node_15/Processor_59, rack_1/BladeEnclosure_2/Node_15/Processor_58, rack_1/BladeEnclosure_2/Node_15/Processor_57];0;null;
+16;16;-1;cluster;4;1225668600;1225690200;1225690200;1225668600;1225668600;23400;1800;21600;1800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_16];[rack_1/BladeEnclosure_2/Node_16/Processor_64, rack_1/BladeEnclosure_2/Node_16/Processor_61, rack_1/BladeEnclosure_2/Node_16/Processor_63, rack_1/BladeEnclosure_2/Node_16/Processor_62];0;null;
+17;17;-1;cluster;4;1225668600;1225693800;1225693800;1225668600;1225668600;27000;1800;25200;1800;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_17];[rack_1/BladeEnclosure_2/Node_17/Processor_68, rack_1/BladeEnclosure_2/Node_17/Processor_67, rack_1/BladeEnclosure_2/Node_17/Processor_66, rack_1/BladeEnclosure_2/Node_17/Processor_65];0;null;
+18;18;-1;cluster;4;1225670400;1225684800;1225684800;1225670400;1225670400;18000;3600;14400;3600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_18];[rack_1/BladeEnclosure_2/Node_18/Processor_69, rack_1/BladeEnclosure_2/Node_18/Processor_70, rack_1/BladeEnclosure_2/Node_18/Processor_72, rack_1/BladeEnclosure_2/Node_18/Processor_71];0;null;
+19;19;-1;cluster;4;1225670400;1225681200;1225681200;1225670400;1225670400;14400;3600;10800;3600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_19];[rack_1/BladeEnclosure_2/Node_19/Processor_73, rack_1/BladeEnclosure_2/Node_19/Processor_76, rack_1/BladeEnclosure_2/Node_19/Processor_75, rack_1/BladeEnclosure_2/Node_19/Processor_74];0;null;
 20;20;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_20];[rack_1/BladeEnclosure_2/Node_20/Processor_78, rack_1/BladeEnclosure_2/Node_20/Processor_79, rack_1/BladeEnclosure_2/Node_20/Processor_77, rack_1/BladeEnclosure_2/Node_20/Processor_80];0;null;
-21;21;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_21];[rack_1/BladeEnclosure_2/Node_21/Processor_84, rack_1/BladeEnclosure_2/Node_21/Processor_83, rack_1/BladeEnclosure_2/Node_21/Processor_82, rack_1/BladeEnclosure_2/Node_21/Processor_81];0;null;
-22;22;-1;cluster;4;1225670400;1225684800;1225684800;1225670400;1225670400;18000;3600;14400;3600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_22];[rack_1/BladeEnclosure_2/Node_22/Processor_88, rack_1/BladeEnclosure_2/Node_22/Processor_87, rack_1/BladeEnclosure_2/Node_22/Processor_86, rack_1/BladeEnclosure_2/Node_22/Processor_85];0;null;
-23;23;-1;cluster;4;1225670400;1225681200;1225681200;1225670400;1225670400;14400;3600;10800;3600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_23];[rack_1/BladeEnclosure_2/Node_23/Processor_89, rack_1/BladeEnclosure_2/Node_23/Processor_92, rack_1/BladeEnclosure_2/Node_23/Processor_91, rack_1/BladeEnclosure_2/Node_23/Processor_90];0;null;
-24;24;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_24];[rack_1/BladeEnclosure_2/Node_24/Processor_96, rack_1/BladeEnclosure_2/Node_24/Processor_94, rack_1/BladeEnclosure_2/Node_24/Processor_95, rack_1/BladeEnclosure_2/Node_24/Processor_93];0;null;
-25;25;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_25];[rack_1/BladeEnclosure_2/Node_25/Processor_99, rack_1/BladeEnclosure_2/Node_25/Processor_100, rack_1/BladeEnclosure_2/Node_25/Processor_97, rack_1/BladeEnclosure_2/Node_25/Processor_98];0;null;
-26;26;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_1];[rack_1/BladeEnclosure_1/Node_1/Processor_2, rack_1/BladeEnclosure_1/Node_1/Processor_1, rack_1/BladeEnclosure_1/Node_1/Processor_4, rack_1/BladeEnclosure_1/Node_1/Processor_3];0;null;
-27;27;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_3];[rack_1/BladeEnclosure_1/Node_3/Processor_12, rack_1/BladeEnclosure_1/Node_3/Processor_10, rack_1/BladeEnclosure_1/Node_3/Processor_11, rack_1/BladeEnclosure_1/Node_3/Processor_9];0;null;
-28;28;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_4];[rack_1/BladeEnclosure_1/Node_4/Processor_16, rack_1/BladeEnclosure_1/Node_4/Processor_15, rack_1/BladeEnclosure_1/Node_4/Processor_14, rack_1/BladeEnclosure_1/Node_4/Processor_13];0;null;
-29;29;-1;cluster;4;1225674000;1225684800;1225684800;1225674000;1225674000;18000;7200;10800;7200;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_5];[rack_1/BladeEnclosure_1/Node_5/Processor_20, rack_1/BladeEnclosure_1/Node_5/Processor_19, rack_1/BladeEnclosure_1/Node_5/Processor_18, rack_1/BladeEnclosure_1/Node_5/Processor_17];0;null;
-30;30;-1;cluster;4;1225677600;1225684800;1225684800;1225677600;1225677600;18000;10800;7200;10800;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_6];[rack_1/BladeEnclosure_1/Node_6/Processor_24, rack_1/BladeEnclosure_1/Node_6/Processor_22, rack_1/BladeEnclosure_1/Node_6/Processor_23, rack_1/BladeEnclosure_1/Node_6/Processor_21];0;null;
-31;31;-1;cluster;4;1225675800;1225686600;1225686600;1225675800;1225675800;19800;9000;10800;9000;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_9];[rack_1/BladeEnclosure_1/Node_9/Processor_33, rack_1/BladeEnclosure_1/Node_9/Processor_35, rack_1/BladeEnclosure_1/Node_9/Processor_34, rack_1/BladeEnclosure_1/Node_9/Processor_36];0;null;
-32;32;-1;cluster;4;1225675800;1225683000;1225683000;1225675800;1225675800;16200;9000;7200;9000;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_13];[rack_1/BladeEnclosure_1/Node_13/Processor_51, rack_1/BladeEnclosure_1/Node_13/Processor_52, rack_1/BladeEnclosure_1/Node_13/Processor_50, rack_1/BladeEnclosure_1/Node_13/Processor_49];0;null;
-33;33;-1;cluster;4;1225675800;1225686600;1225686600;1225675800;1225675800;19800;9000;10800;9000;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_26];[rack_1/BladeEnclosure_2/Node_26/Processor_102, rack_1/BladeEnclosure_2/Node_26/Processor_103, rack_1/BladeEnclosure_2/Node_26/Processor_104, rack_1/BladeEnclosure_2/Node_26/Processor_101];0;null;
-34;34;-1;cluster;4;1225676400;1225690800;1225690800;1225676400;1225676400;24000;9600;14400;9600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_27];[rack_1/BladeEnclosure_2/Node_27/Processor_106, rack_1/BladeEnclosure_2/Node_27/Processor_105, rack_1/BladeEnclosure_2/Node_27/Processor_108, rack_1/BladeEnclosure_2/Node_27/Processor_107];0;null;
-35;35;-1;cluster;4;1225676400;1225690800;1225690800;1225676400;1225676400;24000;9600;14400;9600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_28];[rack_1/BladeEnclosure_2/Node_28/Processor_110, rack_1/BladeEnclosure_2/Node_28/Processor_111, rack_1/BladeEnclosure_2/Node_28/Processor_112, rack_1/BladeEnclosure_2/Node_28/Processor_109];0;null;
-36;36;-1;cluster;4;1225677600;1225706400;1225706400;1225677600;1225677600;39600;10800;28800;10800;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_10];[rack_1/BladeEnclosure_1/Node_10/Processor_40, rack_1/BladeEnclosure_1/Node_10/Processor_37, rack_1/BladeEnclosure_1/Node_10/Processor_38, rack_1/BladeEnclosure_1/Node_10/Processor_39];0;null;
-37;37;-1;cluster;4;1225677600;1225684800;1225684800;1225677600;1225677600;18000;10800;7200;10800;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_20];[rack_1/BladeEnclosure_2/Node_20/Processor_78, rack_1/BladeEnclosure_2/Node_20/Processor_79, rack_1/BladeEnclosure_2/Node_20/Processor_77, rack_1/BladeEnclosure_2/Node_20/Processor_80];0;null;
-38;38;-1;cluster;4;1225677600;1225699200;1225699200;1225677600;1225677600;32400;10800;21600;10800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_21];[rack_1/BladeEnclosure_2/Node_21/Processor_84, rack_1/BladeEnclosure_2/Node_21/Processor_83, rack_1/BladeEnclosure_2/Node_21/Processor_82, rack_1/BladeEnclosure_2/Node_21/Processor_81];0;null;
-39;39;-1;cluster;4;1225677600;1225706400;1225706400;1225677600;1225677600;39600;10800;28800;10800;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_24];[rack_1/BladeEnclosure_2/Node_24/Processor_96, rack_1/BladeEnclosure_2/Node_24/Processor_94, rack_1/BladeEnclosure_2/Node_24/Processor_95, rack_1/BladeEnclosure_2/Node_24/Processor_93];0;null;
-41;41;-1;cluster;4;1225677600;1225699200;1225699200;1225677600;1225677600;32400;10800;21600;10800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_25];[rack_1/BladeEnclosure_2/Node_25/Processor_99, rack_1/BladeEnclosure_2/Node_25/Processor_100, rack_1/BladeEnclosure_2/Node_25/Processor_97, rack_1/BladeEnclosure_2/Node_25/Processor_98];0;null;
-42;42;-1;cluster;4;1225678400;1225703600;1225703600;1225678400;1225678400;36800;11600;25200;11600;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_29];[rack_1/BladeEnclosure_3/Node_29/Processor_115, rack_1/BladeEnclosure_3/Node_29/Processor_116, rack_1/BladeEnclosure_3/Node_29/Processor_113, rack_1/BladeEnclosure_3/Node_29/Processor_114];0;null;
-43;43;-1;cluster;4;1225678400;1225692800;1225692800;1225678400;1225678400;26000;11600;14400;11600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_30];[rack_1/BladeEnclosure_3/Node_30/Processor_119, rack_1/BladeEnclosure_3/Node_30/Processor_118, rack_1/BladeEnclosure_3/Node_30/Processor_117, rack_1/BladeEnclosure_3/Node_30/Processor_120];0;null;
-44;44;-1;cluster;4;1225678400;1225685600;1225685600;1225678400;1225678400;18800;11600;7200;11600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_31];[rack_1/BladeEnclosure_3/Node_31/Processor_121, rack_1/BladeEnclosure_3/Node_31/Processor_122, rack_1/BladeEnclosure_3/Node_31/Processor_123, rack_1/BladeEnclosure_3/Node_31/Processor_124];0;null;
-45;45;-1;cluster;4;1225678400;1225703600;1225703600;1225678400;1225678400;36800;11600;25200;11600;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_32];[rack_1/BladeEnclosure_3/Node_32/Processor_126, rack_1/BladeEnclosure_3/Node_32/Processor_127, rack_1/BladeEnclosure_3/Node_32/Processor_125, rack_1/BladeEnclosure_3/Node_32/Processor_128];0;null;
-46;46;-1;cluster;4;1225678400;1225692800;1225692800;1225678400;1225678400;26000;11600;14400;11600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_33];[rack_1/BladeEnclosure_3/Node_33/Processor_129, rack_1/BladeEnclosure_3/Node_33/Processor_131, rack_1/BladeEnclosure_3/Node_33/Processor_130, rack_1/BladeEnclosure_3/Node_33/Processor_132];0;null;
-47;47;-1;cluster;4;1225678400;1225689200;1225689200;1225678400;1225678400;22400;11600;10800;11600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_34];[rack_1/BladeEnclosure_3/Node_34/Processor_133, rack_1/BladeEnclosure_3/Node_34/Processor_134, rack_1/BladeEnclosure_3/Node_34/Processor_135, rack_1/BladeEnclosure_3/Node_34/Processor_136];0;null;
-48;48;-1;cluster;4;1225679000;1225704200;1225704200;1225679000;1225679000;37400;12200;25200;12200;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_35];[rack_1/BladeEnclosure_3/Node_35/Processor_140, rack_1/BladeEnclosure_3/Node_35/Processor_137, rack_1/BladeEnclosure_3/Node_35/Processor_139, rack_1/BladeEnclosure_3/Node_35/Processor_138];0;null;
-49;49;-1;cluster;4;1225679000;1225686200;1225686200;1225679000;1225679000;19400;12200;7200;12200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_36];[rack_1/BladeEnclosure_3/Node_36/Processor_142, rack_1/BladeEnclosure_3/Node_36/Processor_143, rack_1/BladeEnclosure_3/Node_36/Processor_144, rack_1/BladeEnclosure_3/Node_36/Processor_141];0;null;
-50;50;-1;cluster;4;1225679000;1225689800;1225689800;1225679000;1225679000;23000;12200;10800;12200;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_37];[rack_1/BladeEnclosure_3/Node_37/Processor_145, rack_1/BladeEnclosure_3/Node_37/Processor_146, rack_1/BladeEnclosure_3/Node_37/Processor_147, rack_1/BladeEnclosure_3/Node_37/Processor_148];0;null;
+21;21;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_21];[rack_1/BladeEnclosure_2/Node_21/Processor_84, rack_1/BladeEnclosure_2/Node_21/Processor_81, rack_1/BladeEnclosure_2/Node_21/Processor_82, rack_1/BladeEnclosure_2/Node_21/Processor_83];0;null;
+22;22;-1;cluster;4;1225670400;1225684800;1225684800;1225670400;1225670400;18000;3600;14400;3600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_22];[rack_1/BladeEnclosure_2/Node_22/Processor_87, rack_1/BladeEnclosure_2/Node_22/Processor_88, rack_1/BladeEnclosure_2/Node_22/Processor_85, rack_1/BladeEnclosure_2/Node_22/Processor_86];0;null;
+23;23;-1;cluster;4;1225670400;1225681200;1225681200;1225670400;1225670400;14400;3600;10800;3600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_23];[rack_1/BladeEnclosure_2/Node_23/Processor_92, rack_1/BladeEnclosure_2/Node_23/Processor_91, rack_1/BladeEnclosure_2/Node_23/Processor_90, rack_1/BladeEnclosure_2/Node_23/Processor_89];0;null;
+24;24;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_24];[rack_1/BladeEnclosure_2/Node_24/Processor_95, rack_1/BladeEnclosure_2/Node_24/Processor_94, rack_1/BladeEnclosure_2/Node_24/Processor_96, rack_1/BladeEnclosure_2/Node_24/Processor_93];0;null;
+25;25;-1;cluster;4;1225670400;1225677600;1225677600;1225670400;1225670400;10800;3600;7200;3600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_25];[rack_1/BladeEnclosure_2/Node_25/Processor_100, rack_1/BladeEnclosure_2/Node_25/Processor_98, rack_1/BladeEnclosure_2/Node_25/Processor_97, rack_1/BladeEnclosure_2/Node_25/Processor_99];0;null;
+26;26;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_1];[rack_1/BladeEnclosure_1/Node_1/Processor_4, rack_1/BladeEnclosure_1/Node_1/Processor_3, rack_1/BladeEnclosure_1/Node_1/Processor_2, rack_1/BladeEnclosure_1/Node_1/Processor_1];0;null;
+27;27;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_3];[rack_1/BladeEnclosure_1/Node_3/Processor_10, rack_1/BladeEnclosure_1/Node_3/Processor_11, rack_1/BladeEnclosure_1/Node_3/Processor_12, rack_1/BladeEnclosure_1/Node_3/Processor_9];0;null;
+28;28;-1;cluster;4;1225674000;1225681200;1225681200;1225674000;1225674000;14400;7200;7200;7200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_4];[rack_1/BladeEnclosure_1/Node_4/Processor_15, rack_1/BladeEnclosure_1/Node_4/Processor_16, rack_1/BladeEnclosure_1/Node_4/Processor_13, rack_1/BladeEnclosure_1/Node_4/Processor_14];0;null;
+29;29;-1;cluster;4;1225674000;1225684800;1225684800;1225674000;1225674000;18000;7200;10800;7200;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_5];[rack_1/BladeEnclosure_1/Node_5/Processor_20, rack_1/BladeEnclosure_1/Node_5/Processor_17, rack_1/BladeEnclosure_1/Node_5/Processor_18, rack_1/BladeEnclosure_1/Node_5/Processor_19];0;null;
+30;30;-1;cluster;4;1225675800;1225683000;1225683000;1225675800;1225675800;16200;9000;7200;9000;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_9];[rack_1/BladeEnclosure_1/Node_9/Processor_33, rack_1/BladeEnclosure_1/Node_9/Processor_36, rack_1/BladeEnclosure_1/Node_9/Processor_35, rack_1/BladeEnclosure_1/Node_9/Processor_34];0;null;
+31;31;-1;cluster;4;1225675800;1225686600;1225686600;1225675800;1225675800;19800;9000;10800;9000;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_13];[rack_1/BladeEnclosure_1/Node_13/Processor_51, rack_1/BladeEnclosure_1/Node_13/Processor_52, rack_1/BladeEnclosure_1/Node_13/Processor_50, rack_1/BladeEnclosure_1/Node_13/Processor_49];0;null;
+32;32;-1;cluster;4;1225675800;1225683000;1225683000;1225675800;1225675800;16200;9000;7200;9000;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_26];[rack_1/BladeEnclosure_2/Node_26/Processor_102, rack_1/BladeEnclosure_2/Node_26/Processor_103, rack_1/BladeEnclosure_2/Node_26/Processor_104, rack_1/BladeEnclosure_2/Node_26/Processor_101];0;null;
+33;33;-1;cluster;4;1225675800;1225686600;1225686600;1225675800;1225675800;19800;9000;10800;9000;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_27];[rack_1/BladeEnclosure_2/Node_27/Processor_108, rack_1/BladeEnclosure_2/Node_27/Processor_107, rack_1/BladeEnclosure_2/Node_27/Processor_106, rack_1/BladeEnclosure_2/Node_27/Processor_105];0;null;
+34;34;-1;cluster;4;1225676400;1225690800;1225690800;1225676400;1225676400;24000;9600;14400;9600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_28];[rack_1/BladeEnclosure_2/Node_28/Processor_110, rack_1/BladeEnclosure_2/Node_28/Processor_111, rack_1/BladeEnclosure_2/Node_28/Processor_112, rack_1/BladeEnclosure_2/Node_28/Processor_109];0;null;
+35;35;-1;cluster;4;1225676400;1225690800;1225690800;1225676400;1225676400;24000;9600;14400;9600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_29];[rack_1/BladeEnclosure_3/Node_29/Processor_116, rack_1/BladeEnclosure_3/Node_29/Processor_115, rack_1/BladeEnclosure_3/Node_29/Processor_114, rack_1/BladeEnclosure_3/Node_29/Processor_113];0;null;
+36;36;-1;cluster;4;1225677600;1225706400;1225706400;1225677600;1225677600;39600;10800;28800;10800;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_6];[rack_1/BladeEnclosure_1/Node_6/Processor_21, rack_1/BladeEnclosure_1/Node_6/Processor_23, rack_1/BladeEnclosure_1/Node_6/Processor_22, rack_1/BladeEnclosure_1/Node_6/Processor_24];0;null;
+37;37;-1;cluster;4;1225677600;1225684800;1225684800;1225677600;1225677600;18000;10800;7200;10800;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_1/Node_10];[rack_1/BladeEnclosure_1/Node_10/Processor_40, rack_1/BladeEnclosure_1/Node_10/Processor_37, rack_1/BladeEnclosure_1/Node_10/Processor_39, rack_1/BladeEnclosure_1/Node_10/Processor_38];0;null;
+38;38;-1;cluster;4;1225677600;1225699200;1225699200;1225677600;1225677600;32400;10800;21600;10800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_20];[rack_1/BladeEnclosure_2/Node_20/Processor_78, rack_1/BladeEnclosure_2/Node_20/Processor_79, rack_1/BladeEnclosure_2/Node_20/Processor_77, rack_1/BladeEnclosure_2/Node_20/Processor_80];0;null;
+39;39;-1;cluster;4;1225677600;1225706400;1225706400;1225677600;1225677600;39600;10800;28800;10800;0;28800;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_21];[rack_1/BladeEnclosure_2/Node_21/Processor_84, rack_1/BladeEnclosure_2/Node_21/Processor_81, rack_1/BladeEnclosure_2/Node_21/Processor_82, rack_1/BladeEnclosure_2/Node_21/Processor_83];0;null;
+40;40;-1;cluster;4;1225677600;1225684800;1225684800;1225677600;1225677600;18000;10800;7200;10800;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_24];[rack_1/BladeEnclosure_2/Node_24/Processor_95, rack_1/BladeEnclosure_2/Node_24/Processor_94, rack_1/BladeEnclosure_2/Node_24/Processor_96, rack_1/BladeEnclosure_2/Node_24/Processor_93];0;null;
+41;41;-1;cluster;4;1225677600;1225699200;1225699200;1225677600;1225677600;32400;10800;21600;10800;0;21600;0;0;0;0;0;0;[rack_1/BladeEnclosure_2/Node_25];[rack_1/BladeEnclosure_2/Node_25/Processor_100, rack_1/BladeEnclosure_2/Node_25/Processor_98, rack_1/BladeEnclosure_2/Node_25/Processor_97, rack_1/BladeEnclosure_2/Node_25/Processor_99];0;null;
+42;42;-1;cluster;4;1225678400;1225703600;1225703600;1225678400;1225678400;36800;11600;25200;11600;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_30];[rack_1/BladeEnclosure_3/Node_30/Processor_120, rack_1/BladeEnclosure_3/Node_30/Processor_117, rack_1/BladeEnclosure_3/Node_30/Processor_118, rack_1/BladeEnclosure_3/Node_30/Processor_119];0;null;
+43;43;-1;cluster;4;1225678400;1225692800;1225692800;1225678400;1225678400;26000;11600;14400;11600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_31];[rack_1/BladeEnclosure_3/Node_31/Processor_123, rack_1/BladeEnclosure_3/Node_31/Processor_124, rack_1/BladeEnclosure_3/Node_31/Processor_121, rack_1/BladeEnclosure_3/Node_31/Processor_122];0;null;
+44;44;-1;cluster;4;1225678400;1225685600;1225685600;1225678400;1225678400;18800;11600;7200;11600;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_32];[rack_1/BladeEnclosure_3/Node_32/Processor_125, rack_1/BladeEnclosure_3/Node_32/Processor_127, rack_1/BladeEnclosure_3/Node_32/Processor_126, rack_1/BladeEnclosure_3/Node_32/Processor_128];0;null;
+45;45;-1;cluster;4;1225678400;1225703600;1225703600;1225678400;1225678400;36800;11600;25200;11600;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_33];[rack_1/BladeEnclosure_3/Node_33/Processor_131, rack_1/BladeEnclosure_3/Node_33/Processor_130, rack_1/BladeEnclosure_3/Node_33/Processor_132, rack_1/BladeEnclosure_3/Node_33/Processor_129];0;null;
+46;46;-1;cluster;4;1225678400;1225692800;1225692800;1225678400;1225678400;26000;11600;14400;11600;0;14400;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_34];[rack_1/BladeEnclosure_3/Node_34/Processor_133, rack_1/BladeEnclosure_3/Node_34/Processor_134, rack_1/BladeEnclosure_3/Node_34/Processor_135, rack_1/BladeEnclosure_3/Node_34/Processor_136];0;null;
+47;47;-1;cluster;4;1225678400;1225689200;1225689200;1225678400;1225678400;22400;11600;10800;11600;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_35];[rack_1/BladeEnclosure_3/Node_35/Processor_137, rack_1/BladeEnclosure_3/Node_35/Processor_138, rack_1/BladeEnclosure_3/Node_35/Processor_139, rack_1/BladeEnclosure_3/Node_35/Processor_140];0;null;
+48;48;-1;cluster;4;1225679000;1225704200;1225704200;1225679000;1225679000;37400;12200;25200;12200;0;25200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_36];[rack_1/BladeEnclosure_3/Node_36/Processor_141, rack_1/BladeEnclosure_3/Node_36/Processor_144, rack_1/BladeEnclosure_3/Node_36/Processor_143, rack_1/BladeEnclosure_3/Node_36/Processor_142];0;null;
+49;49;-1;cluster;4;1225679000;1225686200;1225686200;1225679000;1225679000;19400;12200;7200;12200;0;7200;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_37];[rack_1/BladeEnclosure_3/Node_37/Processor_147, rack_1/BladeEnclosure_3/Node_37/Processor_148, rack_1/BladeEnclosure_3/Node_37/Processor_145, rack_1/BladeEnclosure_3/Node_37/Processor_146];0;null;
+50;50;-1;cluster;4;1225679000;1225689800;1225689800;1225679000;1225679000;23000;12200;10800;12200;0;10800;0;0;0;0;0;0;[rack_1/BladeEnclosure_3/Node_38];[rack_1/BladeEnclosure_3/Node_38/Processor_151, rack_1/BladeEnclosure_3/Node_38/Processor_152, rack_1/BladeEnclosure_3/Node_38/Processor_150, rack_1/BladeEnclosure_3/Node_38/Processor_149];0;null;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceOccupancy.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceOccupancy.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_ResourceOccupancy.txt	(revision 1559)
@@ -3,10 +3,10 @@
 utlization;rack_1;1225670400000;0.298;
 utlization;rack_1;1225674000000;0.274;
-utlization;rack_1;1225675800000;0.31;
-utlization;rack_1;1225676400000;0.333;
-utlization;rack_1;1225677600000;0.333;
-utlization;rack_1;1225678400000;0.405;
-utlization;rack_1;1225679000000;0.44;
-utlization;rack_1;1225681200000;0.357;
+utlization;rack_1;1225675800000;0.321;
+utlization;rack_1;1225676400000;0.345;
+utlization;rack_1;1225677600000;0.345;
+utlization;rack_1;1225678400000;0.417;
+utlization;rack_1;1225679000000;0.452;
+utlization;rack_1;1225681200000;0.369;
 utlization;rack_1;1225683000000;0.345;
 utlization;rack_1;1225684800000;0.286;
@@ -25,5 +25,5 @@
 utlization;rack_1;1225704200000;0.024;
 utlization;rack_1;1225706400000;0;
-mean: 0.20995670995670995
+mean: 0.2121212121212121
 utlization;rack_1/BladeEnclosure_1;1225666800000;0.929;
 utlization;rack_1/BladeEnclosure_1;1225668600000;1;
@@ -42,28 +42,31 @@
 utlization;rack_1/BladeEnclosure_2;1225668600000;0.214;
 utlization;rack_1/BladeEnclosure_2;1225670400000;0.786;
-utlization;rack_1/BladeEnclosure_2;1225675800000;0.857;
+utlization;rack_1/BladeEnclosure_2;1225675800000;0.929;
 utlization;rack_1/BladeEnclosure_2;1225676400000;1;
 utlization;rack_1/BladeEnclosure_2;1225677600000;1;
 utlization;rack_1/BladeEnclosure_2;1225681200000;0.857;
-utlization;rack_1/BladeEnclosure_2;1225684800000;0.643;
-utlization;rack_1/BladeEnclosure_2;1225686600000;0.571;
-utlization;rack_1/BladeEnclosure_2;1225690200000;0.5;
+utlization;rack_1/BladeEnclosure_2;1225683000000;0.786;
+utlization;rack_1/BladeEnclosure_2;1225684800000;0.571;
+utlization;rack_1/BladeEnclosure_2;1225686600000;0.5;
+utlization;rack_1/BladeEnclosure_2;1225690200000;0.429;
 utlization;rack_1/BladeEnclosure_2;1225690800000;0.357;
 utlization;rack_1/BladeEnclosure_2;1225693800000;0.214;
 utlization;rack_1/BladeEnclosure_2;1225699200000;0.071;
 utlization;rack_1/BladeEnclosure_2;1225706400000;0;
-mean: 0.48701298701298695
+mean: 0.474025974025974
 utlization;rack_1/BladeEnclosure_3;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3;1225678400000;0.429;
-utlization;rack_1/BladeEnclosure_3;1225679000000;0.643;
-utlization;rack_1/BladeEnclosure_3;1225685600000;0.571;
-utlization;rack_1/BladeEnclosure_3;1225686200000;0.5;
-utlization;rack_1/BladeEnclosure_3;1225689200000;0.429;
-utlization;rack_1/BladeEnclosure_3;1225689800000;0.357;
+utlization;rack_1/BladeEnclosure_3;1225676400000;0.071;
+utlization;rack_1/BladeEnclosure_3;1225678400000;0.5;
+utlization;rack_1/BladeEnclosure_3;1225679000000;0.714;
+utlization;rack_1/BladeEnclosure_3;1225685600000;0.643;
+utlization;rack_1/BladeEnclosure_3;1225686200000;0.571;
+utlization;rack_1/BladeEnclosure_3;1225689200000;0.5;
+utlization;rack_1/BladeEnclosure_3;1225689800000;0.429;
+utlization;rack_1/BladeEnclosure_3;1225690800000;0.357;
 utlization;rack_1/BladeEnclosure_3;1225692800000;0.214;
 utlization;rack_1/BladeEnclosure_3;1225703600000;0.071;
 utlization;rack_1/BladeEnclosure_3;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3;1225706400000;0;
-mean: 0.2532467532467532
+mean: 0.2792207792207792
 utlization;rack_1/BladeEnclosure_4;1225666800000;0;
 utlization;rack_1/BladeEnclosure_4;1225706400000;0;
@@ -101,7 +104,6 @@
 utlization;rack_1/BladeEnclosure_1/Node_6;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_6;1225677600000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_7;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_7;1225681200000;0;
@@ -115,11 +117,12 @@
 utlization;rack_1/BladeEnclosure_1/Node_9;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_10;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_10;1225677600000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_11;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_11;1225681200000;0;
@@ -133,7 +136,7 @@
 utlization;rack_1/BladeEnclosure_1/Node_13;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_14;1225666800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_14;1225668600000;1;
@@ -169,13 +172,12 @@
 utlization;rack_1/BladeEnclosure_2/Node_20;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_20;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_21;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_21;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909092
 utlization;rack_1/BladeEnclosure_2/Node_22;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_22;1225670400000;1;
@@ -191,6 +193,7 @@
 utlization;rack_1/BladeEnclosure_2/Node_24;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_24;1225677600000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24;1225706400000;0;
-mean: 0.9090909090909092
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_25;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_25;1225670400000;1;
@@ -201,12 +204,12 @@
 utlization;rack_1/BladeEnclosure_2/Node_26;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_27;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_28;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_28;1225676400000;1;
@@ -215,51 +218,53 @@
 mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_30;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_31;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_32;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_33;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_34;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_35;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_36;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_37;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_38;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_39;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_39;1225706400000;0;
@@ -498,22 +503,18 @@
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225677600000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_21;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225677600000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_22;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225677600000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_23;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225677600000;1;
-utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_6/Processor_24;1225706400000;0;
-mean: 0.45454545454545453
+mean: 1.0
 utlization;rack_1/BladeEnclosure_1/Node_7/Processor_25;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_7/Processor_25;1225681200000;0;
@@ -551,41 +552,45 @@
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_33;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_34;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_35;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225686600000;0;
+utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225683000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_9/Processor_36;1225706400000;0;
-mean: 0.45454545454545453
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225677600000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_37;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225677600000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_38;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225677600000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_39;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225677600000;1;
+utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225684800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_10/Processor_40;1225706400000;0;
-mean: 1.0
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_11/Processor_41;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_11/Processor_41;1225681200000;0;
@@ -623,25 +628,25 @@
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_49;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_50;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_51;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225666800000;1;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225674000000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225675800000;1;
-utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225683000000;0;
+utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225686600000;0;
 utlization;rack_1/BladeEnclosure_1/Node_13/Processor_52;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.45454545454545453
 utlization;rack_1/BladeEnclosure_1/Node_14/Processor_53;1225666800000;0;
 utlization;rack_1/BladeEnclosure_1/Node_14/Processor_53;1225668600000;1;
@@ -767,49 +772,45 @@
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_77;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_78;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_79;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225684800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_20/Processor_80;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.7272727272727273
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_81;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909092
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_82;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909092
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_83;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909092
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225677600000;1;
-utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225699200000;0;
 utlization;rack_1/BladeEnclosure_2/Node_21/Processor_84;1225706400000;0;
-mean: 0.7272727272727273
+mean: 0.9090909090909092
 utlization;rack_1/BladeEnclosure_2/Node_22/Processor_85;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_22/Processor_85;1225670400000;1;
@@ -855,21 +856,25 @@
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225677600000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_93;1225706400000;0;
-mean: 0.9090909090909092
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225677600000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_94;1225706400000;0;
-mean: 0.9090909090909092
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225677600000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_95;1225706400000;0;
-mean: 0.9090909090909092
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225670400000;1;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225677600000;1;
+utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225684800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_24/Processor_96;1225706400000;0;
-mean: 0.9090909090909092
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_2/Node_25/Processor_97;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_25/Processor_97;1225670400000;1;
@@ -898,42 +903,42 @@
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_101;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_102;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_103;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225675800000;1;
-utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225686600000;0;
+utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225683000000;0;
 utlization;rack_1/BladeEnclosure_2/Node_26/Processor_104;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_105;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_106;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_107;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225666800000;0;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225676400000;1;
-utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225690800000;0;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225675800000;1;
+utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225686600000;0;
 utlization;rack_1/BladeEnclosure_2/Node_27/Processor_108;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_2/Node_28/Processor_109;1225666800000;0;
 utlization;rack_1/BladeEnclosure_2/Node_28/Processor_109;1225676400000;1;
@@ -957,195 +962,203 @@
 mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_113;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_114;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_115;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225676400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225690800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_29/Processor_116;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_117;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_118;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_119;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_30/Processor_120;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_121;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_122;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_123;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225685600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_31/Processor_124;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_125;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_126;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_127;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225703600000;0;
+utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225685600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_32/Processor_128;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_129;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_130;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_131;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225692800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225703600000;0;
 utlization;rack_1/BladeEnclosure_3/Node_33/Processor_132;1225706400000;0;
-mean: 0.36363636363636365
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_133;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_134;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_135;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225678400000;1;
-utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225689200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225692800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_34/Processor_136;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.36363636363636365
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_137;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_138;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_139;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225666800000;0;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225704200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225678400000;1;
+utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225689200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_35/Processor_140;1225706400000;0;
-mean: 0.6363636363636364
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_141;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_142;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_143;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225686200000;0;
+utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225704200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_36/Processor_144;1225706400000;0;
-mean: 0.18181818181818182
+mean: 0.6363636363636364
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_145;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_146;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_147;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225679000000;1;
-utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225689800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225686200000;0;
 utlization;rack_1/BladeEnclosure_3/Node_37/Processor_148;1225706400000;0;
-mean: 0.2727272727272727
+mean: 0.18181818181818182
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_149;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_150;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_151;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225666800000;0;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225679000000;1;
+utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225689800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_38/Processor_152;1225706400000;0;
-mean: 0.0
+mean: 0.2727272727272727
 utlization;rack_1/BladeEnclosure_3/Node_39/Processor_153;1225666800000;0;
 utlization;rack_1/BladeEnclosure_3/Node_39/Processor_153;1225706400000;0;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Jobs.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Jobs.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_Jobs.txt	(revision 1559)
@@ -29,5 +29,5 @@
 28;14,400;7,200;0;7,200;0;0;0;0;14,400;
 29;18,000;10,800;0;10,800;0;0;0;0;18,000;
-30;18,000;7,200;0;7,200;0;0;0;0;18,000;
+30;16,200;7,200;0;7,200;0;0;0;0;16,200;
 31;19,800;10,800;0;10,800;0;0;0;0;19,800;
 32;16,200;7,200;0;7,200;0;0;0;0;16,200;
@@ -39,4 +39,5 @@
 38;32,400;21,600;0;21,600;0;0;0;0;32,400;
 39;39,600;28,800;0;28,800;0;0;0;0;39,600;
+40;18,000;7,200;0;7,200;0;0;0;0;18,000;
 41;32,400;21,600;0;21,600;0;0;0;0;32,400;
 42;36,800;25,200;0;25,200;0;0;0;0;36,800;
Index: DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_EnergyUsage.txt
===================================================================
--- DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_EnergyUsage.txt	(revision 1476)
+++ DCWoRMS/branches/coolemall/example/airflowEstimation_result/Stats_Simulation_1_EnergyUsage.txt	(revision 1559)
@@ -20,7 +20,6 @@
 mean: 340.90909090909093 sum: 3750.0000000000005
 powerConsumption;rack_1/BladeEnclosure_1/Node_6;1225666800000;750;
-powerConsumption;rack_1/BladeEnclosure_1/Node_6;1225684800000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_6;1225706400000;0;
-mean: 340.90909090909093 sum: 3750.0000000000005
+mean: 750.0 sum: 8250.0
 powerConsumption;rack_1/BladeEnclosure_1/Node_7;1225666800000;750;
 powerConsumption;rack_1/BladeEnclosure_1/Node_7;1225681200000;0;
@@ -34,10 +33,11 @@
 powerConsumption;rack_1/BladeEnclosure_1/Node_9;1225674000000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_9;1225675800000;750;
-powerConsumption;rack_1/BladeEnclosure_1/Node_9;1225686600000;0;
+powerConsumption;rack_1/BladeEnclosure_1/Node_9;1225683000000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_9;1225706400000;0;
-mean: 340.9090909090909 sum: 3749.9999999999995
+mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_1/Node_10;1225666800000;750;
+powerConsumption;rack_1/BladeEnclosure_1/Node_10;1225684800000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_10;1225706400000;0;
-mean: 750.0 sum: 8250.0
+mean: 340.90909090909093 sum: 3750.0000000000005
 powerConsumption;rack_1/BladeEnclosure_1/Node_11;1225666800000;750;
 powerConsumption;rack_1/BladeEnclosure_1/Node_11;1225681200000;0;
@@ -51,7 +51,7 @@
 powerConsumption;rack_1/BladeEnclosure_1/Node_13;1225674000000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_13;1225675800000;750;
-powerConsumption;rack_1/BladeEnclosure_1/Node_13;1225683000000;0;
+powerConsumption;rack_1/BladeEnclosure_1/Node_13;1225686600000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_13;1225706400000;0;
-mean: 272.72727272727275 sum: 3000.0
+mean: 340.9090909090909 sum: 3749.9999999999995
 powerConsumption;rack_1/BladeEnclosure_1/Node_14;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_1/Node_14;1225668600000;750;
@@ -86,12 +86,11 @@
 powerConsumption;rack_1/BladeEnclosure_2/Node_20;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_20;1225670400000;750;
-powerConsumption;rack_1/BladeEnclosure_2/Node_20;1225684800000;0;
+powerConsumption;rack_1/BladeEnclosure_2/Node_20;1225699200000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_20;1225706400000;0;
-mean: 272.72727272727275 sum: 3000.0
+mean: 545.4545454545455 sum: 6000.0
 powerConsumption;rack_1/BladeEnclosure_2/Node_21;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_21;1225670400000;750;
-powerConsumption;rack_1/BladeEnclosure_2/Node_21;1225699200000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_21;1225706400000;0;
-mean: 545.4545454545455 sum: 6000.0
+mean: 681.8181818181819 sum: 7500.000000000001
 powerConsumption;rack_1/BladeEnclosure_2/Node_22;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_22;1225670400000;750;
@@ -106,6 +105,7 @@
 powerConsumption;rack_1/BladeEnclosure_2/Node_24;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_24;1225670400000;750;
+powerConsumption;rack_1/BladeEnclosure_2/Node_24;1225684800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_24;1225706400000;0;
-mean: 681.8181818181819 sum: 7500.000000000001
+mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_2/Node_25;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_25;1225670400000;750;
@@ -115,12 +115,12 @@
 powerConsumption;rack_1/BladeEnclosure_2/Node_26;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_26;1225675800000;750;
-powerConsumption;rack_1/BladeEnclosure_2/Node_26;1225686600000;0;
+powerConsumption;rack_1/BladeEnclosure_2/Node_26;1225683000000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_26;1225706400000;0;
-mean: 204.54545454545453 sum: 2249.9999999999995
+mean: 136.36363636363637 sum: 1500.0
 powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225666800000;0;
-powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225676400000;750;
-powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225690800000;0;
+powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225675800000;750;
+powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225686600000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_27;1225706400000;0;
-mean: 272.72727272727275 sum: 3000.0
+mean: 204.54545454545453 sum: 2249.9999999999995
 powerConsumption;rack_1/BladeEnclosure_2/Node_28;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_2/Node_28;1225676400000;750;
@@ -129,51 +129,53 @@
 mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225666800000;0;
-powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225703600000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225676400000;750;
+powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225690800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_29;1225706400000;0;
-mean: 477.27272727272725 sum: 5250.0
+mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_30;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_30;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_30;1225692800000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_30;1225703600000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_30;1225706400000;0;
-mean: 272.72727272727275 sum: 3000.0
+mean: 477.27272727272725 sum: 5250.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_31;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_31;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_31;1225685600000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_31;1225692800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_31;1225706400000;0;
-mean: 136.36363636363637 sum: 1500.0
+mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_32;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_32;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_32;1225703600000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_32;1225685600000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_32;1225706400000;0;
-mean: 477.27272727272725 sum: 5250.0
+mean: 136.36363636363637 sum: 1500.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_33;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_33;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_33;1225692800000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_33;1225703600000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_33;1225706400000;0;
-mean: 272.72727272727275 sum: 3000.0
+mean: 477.27272727272725 sum: 5250.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_34;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_34;1225678400000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_34;1225689200000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_34;1225692800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_34;1225706400000;0;
-mean: 204.54545454545453 sum: 2249.9999999999995
+mean: 272.72727272727275 sum: 3000.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225666800000;0;
-powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225679000000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225704200000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225678400000;750;
+powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225689200000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_35;1225706400000;0;
-mean: 477.27272727272725 sum: 5250.0
+mean: 204.54545454545453 sum: 2249.9999999999995
 powerConsumption;rack_1/BladeEnclosure_3/Node_36;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_36;1225679000000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_36;1225686200000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_36;1225704200000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_36;1225706400000;0;
-mean: 136.36363636363637 sum: 1500.0
+mean: 477.27272727272725 sum: 5250.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_37;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_37;1225679000000;750;
-powerConsumption;rack_1/BladeEnclosure_3/Node_37;1225689800000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_37;1225686200000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_37;1225706400000;0;
-mean: 204.54545454545453 sum: 2249.9999999999995
+mean: 136.36363636363637 sum: 1500.0
 powerConsumption;rack_1/BladeEnclosure_3/Node_38;1225666800000;0;
+powerConsumption;rack_1/BladeEnclosure_3/Node_38;1225679000000;750;
+powerConsumption;rack_1/BladeEnclosure_3/Node_38;1225689800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_38;1225706400000;0;
-mean: 0.0 sum: 0.0
+mean: 204.54545454545453 sum: 2249.9999999999995
 powerConsumption;rack_1/BladeEnclosure_3/Node_39;1225666800000;0;
 powerConsumption;rack_1/BladeEnclosure_3/Node_39;1225706400000;0;
